View ATA8202-14_8240710.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

4971g-indco-09/14 features transparent rf receiver ics for 315mhz (atmel ? ata8201) and 433.92mhz (atmel ata8202) with high receiving sensitivity fully integrated pll with low phase noise vco, pll, and loop filter high fsk/ask sensitivity: ?105dbm (atmel ata8201, fsk, 9.6kbits/s, manchester, ber 10 -3 ?114dbm (atmel ata8201, ask, 2.4kbits/s, manchester, ber 10 -3 ) ?104dbm (atmel ata8202, fsk, 9.6kbits/s, manchester, ber 10 -3 ) ?113dbm (atmel ata8202, ask, 2.4kbits/s, manchester, ber 10 -3 ) supply current: 6.5ma in acti ve mode (3v, 25c, ask mode) data rate: 1kbit/s to 10kbits/s manchester ask, 1kbit/s to 20kbits/s manchester fsk with four programmable bit rate ranges switching between modulation types ask/fs k and different data rates possible in 1ms typically, without hardware modification on board to allow different modulation schemes low standby current: 50a at 3v, 25c ask/fsk receiver uses a low-if architecture with high selectivity, blocking, and low intermodulation (typical 3-db blocking 68.0dbc at 3mhz/74.0dbc at 20.0mhz, system i1dbcp = ?31dbm/system iip3 = ?24dbm) telegram pause up to 52ms supported in ask mode wide bandwidth agc to handle large out-of-band blockers above the system i1dbcp 440-khz if frequency with 30-db image rejection and 420-khz if bandwidth to support pll transmitters with standard crystals or saw-based transmitters rssi (received signal strength indicato r) with output signal dynamic range of 65db low in-band sensitivity change of typically 2.0db within 160-khz center frequency change in the complete temperature and supply voltage range sophisticated threshold control and quasi-peak detector circuit in the data slicer fast and stable xto start-up circuit (> ?1.4 k worst-case start impedance) clock generation for microcontroller esd protection at all pins (4kv hbm, 200v mm, 500v fcdm) ata8201/ata8202 uhf ask/fsk receiver datasheet
ata8201/ata8202 [datasheet] 4971g?indco?09/14 2 dual supply voltage range: 2.7v to 3.3v or 4.5v to 5.5v temperature range: ?40c to +85c small 5mm 5mm qfn24 package applications industrial/aftermarket keyless entry and tire pressure monitoring systems alarm, telemetering and energy metering systems remote control systems for consumer and industrial markets access control systems home automation home entertainment to y s benefits supports header and blanking periods of protocols co mmon in rke and tpm systems (up to 52ms in ask mode) all rf relevant functions are integrated. the single-ended rf input is suited for easy adaptation to / 4 or printed-loop antennas allows a low-cost application with only 8 passive components optimal bandwidth maximizes sensitivity while maintaining saw transmitter compatibility clock output provides an external microcontroller crystal-precision time reference well suited for use with atmel ? pll transmitter ata8401/ata8402/ata8403/ata8404/ata8405
3 ata8201/ata8202 [datasheet] 4971g?indco?09/14 1. general description the atmel ? ata8201/ata8202 is a uhf ask/fsk transparent receiver ic with low power consumption supplied in a small qfn24 package (body 5mm 5mm, pitch 0.65mm). atmel ata8202 is used in the 433mhz to 435mhz band of o peration, and atmel ata8201 in 313mhz to 317mhz. for improved image rejection and selectivit y, the if frequency is fixed to 440khz. the if block uses an 8th-order band pass yielding a receive bandwidth of 420khz. this enables the use of the receiver in both saw- and pll-based transmitter systems utilizing various types of data-bit encoding such as pu lse width modulation, manchester modulation, variable pulse modulation, pulse position modulation, and nrz. prevailing encryption protocols such as keeloq ? are easily supported due to the receiver?s ability to hold the current data slicer threshold for up to 52ms when incoming rf telegrams contain a blanking interval. this feature eliminates erroneous noise from appearing on the demodulated dat a output pin, and simplifies software decoding algorithms. the decoding of the data stream must be carried out by a connected microcontroller device. because of the highly integrat ed design, the only required rf components are for the purpose of receiver antenna matching. atmel ata8201 and atmel ata8202 support manchester bit rates of 1kbit/s to 10kbits/s in ask and 1kbit/s to 20kbits/s in fsk mode. the four discrete bit rate passb ands are selectable and cover 1.0kbit/s to 2.5kbits/s, 2.0kbits/s to 5.0kbits/s, 4.0kbits/s to 10.0kbits/s, and 8.0kbits/s to 10.0kbits/s or 20.0kbits/s (for ask or f sk, respectively). the receiver contains an rssi output to provide an indication of received signal st rength and a sense input to allow the customer to select a threshold below which the data signal is gated off. ask/ fsk and bit rate ranges are selected by the connected microcontroller device via pins ask_nfsk, br0, and br1. figure 1-1. system block diagram (lna, mixer, vco, pll, if filter, rssi amp., demodulator) rf receiver ata8201/ata8202 a ntenna xto microcontroller microcontroller interface 4 ... 8 power supply digital control logic
ata8201/ata8202 [datasheet] 4971g?indco?09/14 4 figure 1-2. pinning qfn24 table 1-1. pin description pin symbol function 1 test2 test pin, during operation at gnd 2 test1 test pin, during operation at gnd 3 clk_out output to clock a connected microcontroller 4 clk_out_ctrl1 input to control clk_out (msb) 5 clk_out_ctrl0 input to control clk_out (lsb) 6 enable input to enable the xto 7 xtal2 reference crystal 8 xtal1 reference crystal 9 dvcc digital voltage supply blocking 10 vs5v power supply input for voltage range 4.5v to 5.5v 11 vs3v_avcc power supply input for voltage range 2.7v to 3.3v 12 gnd ground 13 lna_gnd rf ground 14 lna_in rf input 15 sense sensitivity control resistor 16 sense_ctrl sensitivity selection low: normal sensitivity, high: reduced sensitivity 17 rssi output of the rssi amplifier 18 test3 test pin, during operation at gnd 19 rx input to activate the receiver 20 br0 bit rate selection, lsb 21 br1 bit rate selection, msb 22 ask_nfsk fsk/ask selection low: fsk, high: ask 23 cdem capacitor to adjust the lower cut-off frequency data filter 24 data_out data output gnd ground/backplane (exposed die pad) test3 data_out br1 rx br0 ask_nfsk cdem xtal2 vs5v gnd vs3v_avcc dvcc xtal1 rssi lna_in lna_gnd sense sense_ctrl test2 789101112 24 13 14 15 16 17 18 6 5 4 3 2 1 23 22 test1 clk_out_ctrl0 enable clk_out_ctrl1 clk_out 21 20 19
5 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 1-3. block diagram lpf fsk ask vs3v_avcc vs5v sense_ctrl sense gnd dvcc lna_in lna_gnd cdem ask_nfsk br0 br1 rx clk_out_ctrl1 test1 test3 test2 enable rssi clk_out clk_out_ctrl0 data_out standby logic control xto div. by 3, 6, 12 lpf xtal2 xtal1 xto lna vco pll (/24, /32) if amp if amp ask/fsk demo- dulator power supply data slicer ask/fsk control if filter
ata8201/ata8202 [datasheet] 4971g?indco?09/14 6 2. rf receiver as seen in figure 1-3 on page 5 , the rf receiver consists of a low-noise amp lifier (lna), a local oscillator, and the signal processing part with mixer, if filter, if amplifier with analog rssi, fsk/ask demodulator , data filter, an d data slicer. in receive mode, the lna pre-amplifies the received signal which is converted down to a 440-khz intermediate frequency (if), then filtered and amplified before it is fed into an fsk/ask demodulator, data filter, and data slicer. the received sign al strength indicator (rssi) signal is available at the pin rssi. 2.1 low-if receiver the receive path consists of a fully integr ated low-if receiver. it fulfills the sensit ivity, blocking, selectivity, supply vol tage, and supply current specificatio n needed to design, e.g., an industrial/ afte rmarket integrated receiver for rke and tpm systems. a benefit of the integr ated receive filter is that no external components needed. at 315mhz, the atmel ? ata8201 receiver (433.92mhz for the atmel ata8202 receiver) has a typical system noise figure of 6.0db (7.0db), a system i1dbcp of ?31dbm (?30dbm), and a syst em iip3 of ?24dbm (?23dbm). the signal path is linear for out-of-band disturbers up to the i1dbcp and hence there is no agc or switching of the ln a needed, and a better blocking performance is achieved. this receiver us es an if (intermediate frequency) of 440k hz, the typical image rejection is 30db and the typical 3-db if filter bandwidth is 420khz (f if = 440khz 210khz, f lo_if = 230khz and f hi_if = 650khz). the demodulator needs a signal-to-noise rati o of 8.5db for 10kbits/s ma nchester with 38khz frequen cy deviation in fsk mode, thus, the resulting sensitiv ity at 315mhz (433.92mhz) is typically ?105dbm (?104dbm). due to the low phase noise and spurs of t he synthesizer together with the 8th-order integrated if filter, the receiver has a better selectivity and blocking performance than more comp lex double superhet receiver s, without using external components and without numerous spurious receiving frequencies. a low-if architecture is also less sens itive to second-order intermodulation (iip2) than direct conversion receivers where every pulse or amplitude modulated signal (especially the signals from tdma systems like gsm) demodulates to the receiving signal band at second-order non-linearities. 2.2 input matching at lna_in the measured input impedances as well as t he values of a parallel equivalent circuit of these impedances can be seen in table 2-1 . the highest sensitivity is achieved with power matching of these impedances to the source impedance. the matching of the lna input to 50 is done using the circuit shown in figure 2-1 and the values of the matching elements given in table 2-2 . the reflection coefficients were always ?10db. note that value changes of c1 and l1 may be necessary to compensate individual board layout para sitics. the measured typical fsk and ask manchester-code sensitivities with a bit error rate (ber) of 10 ?3 are shown in table 2-3 and table 2-4 on page 7 . these measurements were done with wire-wound inductors havin g quality factors reported in table 2-2 , resulting in estimated matching losses of 0.8db at 315mhz and 433.92mhz. these losses can be estimated when calculating the parallel equivalent resistance of the inductor with r loss =2 f l q l and the matching loss with 10 log(1+r in_p /r loss ). figure 2-1. input matching to 50 table 2-1. measured input impedances of the lna_in pin f rf [mhz] z in (rf_in) [ ] r in_p //c in_p [pf] 315 (72.4 ? j298) 1300 //1.60 433.92 (55 ? j216) 900 //1.60 rf in 14 c1 l1 lna_in ata8201/ata8202
7 ata8201/ata8202 [datasheet] 4971g?indco?09/14 conditions for the sensitivity measurement: the given sensitivity values are valid for manchester-modulated signals. for the sensitivity me asurement the distance from edge to edge must be evaluated. as can be seen in figure 6-1 on page 21 , in a manchester-modulated data stream, the time segments t ee and 2 t ee occur. to reach the specified sensit ivity for the evaluation of t ee and 2 t ee in the data stream, the fo llowing limits should be used (t ee min, t ee max, 2 t ee min, 2 t ee max). table 2-2. input matching to 50 f rf [mhz] c 1 [pf] l 1 [nh] q l1 315 2.2 68 20 433.92 2.2 36 15 table 2-3. measured typi cal sensitivity fsk, 38 khz, manchester, ber = 10 ?3 rf frequency br_range_0 1.0kbit/s br_range_0 2.5kbits/s br_range_1 5kbits/s br_range_2 10kbits/s br_range_3 10kbits/s br_range_3 20kbits/s 315mhz ?108dbm ?108dbm ?107dbm ?105dbm ?104dbm ?104dbm 433.92mhz ?107dbm ?107dbm ?106dbm ?104dbm ?103dbm ?103dbm table 2-4. measured typical sensitivit y 100% ask, manchester, ber = 10 ?3 rf frequency br_range_0 1.0kbit/s br_range_0 2.5kbits/s br_range_1 5kbits/s br_range_2 10kbits/s br_range_3 10kbits/s 315mhz ?114dbm ?114dbm ?113dbm ?111dbm ?109dbm 433.92mhz ?113dbm ?113dbm ?112dbm ?110dbm ?108dbm table 2-5. limits for sensitivity measurements bit rate t ee min t ee typ t ee max 2 t ee min 2 t ee typ 2 t ee max 1.0kbit/s 260s 500s 790s 800s 1000s 1340s 2.4kbits/s 110s 208s 310s 320s 416s 525s 5.0kbits/s 55s 100s 155s 160s 200s 260s 9.6kbits/s 27s 52s 78s 81s 104s 131s
ata8201/ata8202 [datasheet] 4971g?indco?09/14 8 2.3 sensitivity versus supply voltage, temperature and frequency offset to calculate the behavior of a transmission system, it is important to know the reduc tion of the sensitivity due to several influences. the most important are frequency offset due to crystal oscillator (xto) and crystal frequency (xtal) errors, temperature and supply voltage dependency of the noise figure, and if-filter bandwidth of the receiver. figure 2-2 and figure 2-3 on page 8 show the typical sensitivity at 315mhz, a sk, 2.4kbits/s and 9.6kb its/s, manchester, figure 2-4 and figure 2-5 on page 9 show a typical sensitivity at 315mhz, fsk, 2.4kbi ts/s and 9.6kbits/s, 38khz, manchester versus the frequency offset between transmitter and receiver at t amb = +25c and supply voltage vs = vs3v_avcc = vs5v = 3.0v. figure 2-2. measured sensitivity (315mhz, ask, 2. 4kbits/s, manchester) versus frequency offset figure 2-3. measured sensitivity (315mhz, ask, 9. 6kbits/s, manchester) versus frequency offset -300 -200 -100 0 100 200 300 delta rf (khz) at 315mhz -118 -117 -116 -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 input sensitivity (dbm) input sensitivity (dbm) at ber < 1e-3, at a8201, ask, 2.4kbits/s (manchester), br = 0 3.0v/25c -300 -200 -100 0 100 200 300 delta rf (khz) at 315mhz -115 -114 -113 -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 input sensitivity (dbm) input sensitivity (dbm) at ber < 1e-3, at a8201, ask, 9.6kbits/s (manchester), br = 2 3.0v/25c
9 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 2-4. measured sensitivity (315m hz, fsk, 2.4kbits/s, 38khz, manchester) versus frequency offset figure 2-5. measured sensitivity (315m hz, fsk, 9.6kbits/s, 38khz, manchester) versus frequency offset as can be seen in figure 2-5 on page 9 , the supply voltage has almost no influenc e. the temperature has an influence of about 1.0db, and a frequency offset of 160khz also influe nces by about 1db. all thes e influences, combined with the sensitivity of a typical ic (?105db), ar e then within a range of ?103.0dbm and ?107.0 dbm over temperature, supply voltage, and frequency offset. the integrated if filter has an additional production tolerance of 10khz, hence, a frequency offset between the receiver and the transmitter of 160 khz can be accepted for xtal and xto tolerances. note: for the demodulator used in the atmel ? ata8201/ata8202, the tolerable fr equency offset does not change with the data frequency. hence, the value of 160khz is valid for 1kbit/s to 10kbits/s. this small sensitivity change over supply vo ltage, frequency offset, and temperature is very unusual in such a receiver. it is achieved by an internal, very fast, and automatic frequency correc tion in the fsk demodulator af ter the if filter, which leads to a higher system margin. this frequency correction tracks the input frequency very quickly. if, however, the input frequency makes a larger step (for example, if t he system changes between different communic ation partners), the receiver has to be restarted. this can be done by switching back to st andby mode and then again to active mode (pin rx 1 0 1) or by generating a positive pul se on pin ask_nfsk (0 1 0). -300 -200 -100 0 100 200 300 delta rf (khz) at 315mhz -112 -111 -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 input sensitivity (dbm) input sensitivity (dbm) at ber < 1e-3, at a8201, fsk, 2.4kbits/s (manchester), br = 0 3.0v/25c -300 -200 -100 0 100 200 300 delta rf (khz) at 315mhz -110 -109 -108 -107 -106 -105 -104 -103 -102 -101 -100 -99 -98 -97 -96 -95 input sensitivity (dbm) input sensitivity (dbm) at ber < 1e-3, at a8201, fsk, 9.64kbits/s (manchester), br = 2 3.0v/25c
ata8201/ata8202 [datasheet] 4971g?indco?09/14 10 2.4 rx supply current versus temperature and supply voltage table 2-7 shows the typical supply current of the receiver in active mode versus supply voltage and temperature with vs = vs3v_avcc = vs5v. 2.5 blocking, selectivity as can be seen in figure 2-6 on page 10 , and figure 2-7 and figure 2-8 on page 11 , the receiver can receive signals 3db higher than the sensitivity level in the presence of large blockers of ?34.5dbm or ?28dbm with small frequency offsets of 3mhz or 20mhz. figure 2-6 , and figure 2-7 on page 11 show the narrow-band blocking, and figure 2-8 on page 11 shows the wide-band blocking characteristic. the measurements were done with a useful signal of 315mhz , fsk, 10kbits/s, 38khz, manchester, br_range2 with a level of ?105dbm + 3db = ?102dbm, which is 3db above the sensitivity level. the figures show how much larger than ?102dbm a continuous wave signal can be, until the ber is higher than 10 ?3 . the measurements were done at the 50 input shown in figure 2-1 on page 6 . at 3 mhz, for example, the bl ocker can be 67.5dbc higher than ? 102dbm, or ?102dbm + 67.5dbc = ?34.5dbm. figure 2-6. close-in 3-db blocking char acteristic and image response at 315mhz table 2-6. measured current in active mode ask vs = vs3v_avcc = vs5v 3.0v t amb = 25c 6.5ma table 2-7. measured current in active mode fsk vs = vs3v_avcc = vs5v 3.0v t amb = 25c 6.7ma -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 distance from interfering to receiving signal (mhz) 70 60 50 40 30 20 10 0 -10 blocking level (dbc)
11 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 2-7. narrow-band 3-db bloc king characteristic at 315mhz figure 2-8. wide-band 3-db blocki ng characteristic at 315mhz table 2-8 shows the blocking performance measured relative to ?102dbm for some frequencies. note that sometimes the blocking is measured relative to the sensitivity level 104dbm (denoted dbs), instead of the carrier ?102dbm (denoted dbc). the atmel ? ata8201/ata8202 can also receive fsk and ask modulated signals if they are much higher than the i1dbcp. it can typically receive useful signals at ?10dbm. this is often referred to as the nonlinear dynamic range (that is, the maximum to minimum receiving signal), and is 95db for 10kbits/s manchester (fsk). this value is useful if the transmitter and receiver are very close to each other. table 2-8. blocking 3db above se nsitivity level with ber < 10 ?3 frequency offset blocking level blocking +1.5mhz ?44.5dbm 57.5dbc, 60.5dbs ?1.5mhz ?44.5dbm 57.5dbc, 60.5dbs +2mhz ?39.0dbm 63dbc, 66dbs ?2mhz ?36.0dbm 66dbc, 69dbs +3mhz ?34.5dbm 67.5dbc, 70.5dbs ?3mhz ?34.5dbm 67.5dbc, 70.5dbs +20mhz ?28.0dbm 74dbc, 77dbs ?20mhz ?28.0dbm 74dbc, 77dbs -5-4-3-2-1012345 distance from interfering to receiving signal (mhz) 80 70 60 50 40 30 20 10 0 -10 blocking level (dbc) -50 -40 -30 -20 -10 0 10 20 30 40 50 distance from interfering to receiving signal (mhz) 80 70 60 50 40 30 20 10 0 -10 blocking level (dbc)
ata8201/ata8202 [datasheet] 4971g?indco?09/14 12 2.6 in-band disturbers, data filter, quasi-peak detector, data slicer if a disturbing signal falls into the received band, or if a blocker is not a continuous wave, the performance of a receiver strongly depends on the circuits after t he if filter. hence, the de modulator, data filter, and data slicer are important. the data filter of the atmel ? ata8201/ata8202 functions also as a quasi-peak detector. this results in a good suppression of above mentioned distur bers and exhibits a good carrier-to-noise perfo rmance. the required usef ul-signal-to-disturbing- signal ratio, at a ber of 10 ?3, is less than 14db in ask mode and less than 3db (br_range_0 to br_range_2) and 6db (br_range_3) in fsk mode. due to the many different possibl e waveforms, these numbers are measured for the signal, as well as for disturbers, with peak amplitude values. note that these values are worst-ca se values and are valid for any type of modulation and modulating frequency of the di sturbing signal, as well as for the receiving signal. for many combinations, lower carrier-to-disturbing-signal ratios are needed. 2.7 rssi output the output voltage of the pin rssi is an analog voltage, proportional to the input power level. using the rssi output signal, the signal strength of different transmitters can be distingui shed. the usable dynamic range of the rssi amplifier is 65db, the input power range p(rf in ) is ?110dbm to ?45dbm, and the gain is 15mv/db. figure 2-9 shows the rssi characteristic of a typical device at 315mhz with vs3v_avcc = vs5v = 3v and t amb = 25c with a matched input as shown in table 2-2 and figure 2-1 on page 6 . at 433.92mhz, 1 db more signal level is needed for the same rssi results. figure 2-9. typical rssi charac teristic at 315mhz versus temperature and supply voltage as can be seen in figure 2-9 on page 12 , for single devices there is a variance over temperature and supply voltage range of 3db. the total variance over production, temperature, and supply voltage range is 9db. 2.8 frequency synthesizer the lo generates the carrier frequency for the mixer via a pll synthesizer. the xto (crystal oscillator) generates the reference frequency f xto . the vco (voltage-controlled oscillato r) generates the drive voltage frequency f lo for the mixer. f lo is divided by the factor 24 (atmel ata8201) or 32 (atmel ata8202). the divided frequency is compared to f xto by the phase frequency detector. the current output of the phase frequency det ector is connected to the fully integrated loop filter, and thereby generates the control voltage for the vco. by means of that configuration, th e vco is controlled in a way, such that f lo /24 (f lo / 32) is equal to f xto . if f lo is determined, f xto can be calculated using the following formula: f xto =f lo /24 (f xto =f lo / 32). the synthesizer has a phase noise of ?130dbc/hz at 3mhz and spurs of ?75dbc. care must be taken with the harmonics of the clk output signal, as well as with the harmonics produced by a microprocessor clocked using the signal, as thes e harmonics can disturb the reception of signals. -130 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 pin (dbm) 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 v_rssi (v) min: -9dbm max: +9dbm 3v, 25c
13 ata8201/ata8202 [datasheet] 4971g?indco?09/14 3. xto the xto is an amplitude-regulated pierce oscill ator type with external load capacitances (2 16pf). due to additional internal and board parasitics (c p ) of approximately 2pf on each side, the load capacitance amounts to 2 18pf (9pf total). the xto oscillation frequency f xto is the reference frequency for the integer-n synthesizer. when des igning the system in terms of receiving and transmitting frequency offset, the accuracy of the crystal and xto have to be considered. the xto?s additional pulling (including the r m tolerance) is only 5ppm. the xt al versus temperature, aging, and tolerances is then the main source of frequency error in the local oscillator. the xto frequency depends on xtal properties and the load capacitances c l1,2 at pin xtal1 and xtal2. the pulling (p) of f xto from the nominal f xtal is calculated using the following formula: c m , the crystal?s motional capacitance; c 0 , the shunt capacitance; and c ln , the nominal load capacitance of the xtal, are found in the datasheet. c l is the total actual load capacitance of th e crystal in the circuit, and consists of c l1 and c l2 connected in series. figure 3-1. crystal equivalent circuit with c m 10ff, c 0 1.0pf, c ln = 9pf and c l1,2 = 16pf 1%, the pulling amounts to p 1ppm. the c 0 of the xtal has to be lower than c lmin / 2 = 7.9pf for a pierce oscillator type in order to not enter the steep region of pulling versus load capacitance where there is risk of an unstable oscillation. to ensure proper start-up behavior, the small signal gain and th e negative resistance provided by this xto at start is very large. for example, oscillation starts up even in th e worst case with a crystal series resistance of 1.5k at c 0 2.2pf with this xto. the negative resistance is approximately given by with z 1 and z 2 as complex impedances at pins xtal1 and xtal2, hence z 1 =?j/(2 p f xto c l1 )+5 and z 2 =?j/(2 p f xto c l2 )+5 . z 3 consists of crystal c 0 in parallel with an internal 110-k resistor, hence z 3 =?j/(2 p f xto c 0 )/110k , gm is the internal transconductance betw een xtal1 and xtal2, with typically 20ms at 25c. with f xto = 13.5mhz, gm = 20ms, c l = 9pf, and c 0 = 2.2pf, this results in a negative resistance of about 2k . the worst case for technology, supply voltage, and temper ature variations is then always higher than 1.4k for c 0 2.2pf. due to the large gain at start, the xto is able to meet a very low start-up time. the oscillation start-up time can be estimate d with the time constant . p c m 2 ------- c ln c l ? c o c ln + () c o c l + () ------------------------------------------------------------- 10 -6 ppm = c 0 c l2 c l1 c m l m r m c l = c l1 x c l2 / (c l1 + c l2 ) xtal crystal equivalent circuit re zxtocore {} re z 1 z 3 z 2 z 3 z 1 z 3 gm + + z 1 z 2 z 3 z 1 z 2 gm +++ ---------------------------------------------------------------------------------- - ?? ?? ?? = 2 4 2 f xtal 2 c m re z xtocore () r m + () ----------------------------------------------------------------------------------------------------------- - =
ata8201/ata8202 [datasheet] 4971g?indco?09/14 14 after 10 to 20 , an amplitude detector detects the oscillation amplitud e and sets xto_ok to high if the amplitude is large enough; this activates the clk_out output if it is enabled via the pins clk_out_ctrl0 and clk_out_ctrl1. note that the necessary conditions of the dvcc voltage also have to be fulfilled. it is recommended to use a crystal with c m = 3.0ff to 10ff, c ln =9pf, r m < 120 and c 0 = 1.0pf to 2.2pf. lower values of c m can be used, slightly increasing the start-up time. lower values of c 0 or higher values of c m (up to 15ff) can also be used, with only little influence on pulling. figure 3-2. xto block diagram the relationship between f xto and the f rf is shown in table 3-1 . attention must be paid to the harmonics of the clk_out output signal f clk_out as well as to the harmonics produced by an microprocessor clocked with it, since these ha rmonics can disturb the reception of signal s if they get to the rf input. if the clk_out signal is used, it must be carefully laid out on the ap plication pcb. the supply voltage of the microcontroller must also be carefully blocked. table 3-1. calculation of f rf frequency [mhz] f xto [mhz] f rf 433.92 (atmel ata8202) 13.57375 f xto 32 ? 440khz 315.0 (atmel ata8201) 13.1433 f xto 24 ? 440khz c l2 c l1 f dclk f fxto clk_out_ctrl1 clk_out_ctrl0 xto_ok xtal1 xtal2 clk_out amplitude detector divider /16 & divider /3, /6, /12
15 ata8201/ata8202 [datasheet] 4971g?indco?09/14 3.1 pin clk_out pin clk_out is an output to clock a connected microcontroll er. the clock is available in standby and active modes. the frequency f clk_out can be adjusted via the pins clk_out_ctrl0 and clk_out_ctrl1, and is calculated as follows: the signal at clk_out output has a nominal 50% duty cycle. to save current, it is recommended that clk_out be switched off during standby mode. 3.2 basic clock cycle of the digital circuitry the complete timing of the digital circuitry is derived from one clock. as seen in figure 3-2 on page 14 , this clock cycle, t dclk , is derived from the crystal oscillator (xto) in combination with a divider. t dclk controls the following application relevant parameters: - debouncing of the data signal stream - start-up time of the rx signal path the start-up time and the debounce characte ristic depend on the selected bit rate range (br_range) which is defined by pins br0 and br1. the clock cycle t xdclk is defined by the following formulas for further reference: br_range ? br_range 0: t xdclk = 8 t dclk br_range 1: t xdclk = 4 t dclk br_range 2: t xdclk = 2 t dclk br_range 3: t xdclk = 1 t dclk table 3-2. setting of f clk_out clk_out_ctrl1 clk_out_ctrl0 function 0 0 clock on pin clk_out is switched off (low level on pin clk_out) 0 1 f clk_out =f xto /3 1 0 f clk_out =f xto /6 1 1 f clk_out =f xto /12 f dclk f xto 16 ----------- =
ata8201/ata8202 [datasheet] 4971g?indco?09/14 16 4. sensitivity reduction the output voltage of the rssi amplifier is internally compared to a threshold voltage v th_red . v th_red is determined by the value of the external resistor r sense . r sense is connected between the pins sense and vs3v_avcc (see figure 10-1 on page 25 ). the output of the compar ator is fed into the digital control logic. by this means, it is possible to operate the receiver at a lower sensitivity. if the level on input pin sense_ctrl is low, the receiver operates at full sensitivity. if the level on input pin sense_ctrl is high, the receiver operat es at a lower sensitivity. the reduced sensitivity is defined by the value of r sense , the maximum sensitivity by the signal-to-noise rati o of the lna input. the re duced sensitivity depends on the signal strength at the output of the rssi amplifier. since different rf input networks may exhibit slightly different values for the lna gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. this matching is illustrated in figure 2-1 on page 6 and exhibits the best possible sensitivity. if the sensitivity reduction feature is not used, pin sense can be left open, pin sense_ctrl must be set to gnd. to operate with reduced sensit ivity, pin sense_ctrl must be set to high before the rx signal path will be enabled by setting pin rx to high (see figure 4-1 on page 16 ). as long as the rssi level is lower than v th_red (defined by the external resistor r sense ) no data stream is available on pin data_out (low level on pin data_out). an in ternal rs flip-flop will be set to high the fi rst time the rssi voltage crosses v th_red , and from then on the data stream will be available on pin data_out. from then on the receiver also wo rks with full sensitivity. this makes sure that a telegram will not be interrupted if the rssi level varies during the transm ission. the rs flip-flop can be set back, and thus the receiver switched back to reduced sensitivity, by generating a positive pulse on pin ask_nfsk (see figure 4-2 on page 17 ). in fsk mode, operating with reduced sensitivity follows the same way. figure 4-1. reduced sensitivity active rssi rx data_out sense_ctrl ask_nfsk enable t startup_pll v th_red t startup_sig_proc
17 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 4-2. restart reduced sensitivity 5. power supply figure 5-1. power supply the supply voltage range of the atmel ? ata8201/ata8202 is 2.7v to 3.3v or 4.5v to 5.5v. pin vs3v_avcc is the supply voltage input for the range 2.7v to 3.3v, and is used in battery applications using a single lithium 3v cell. pin vs5v is the voltage input for the range 4.5v to 5.5v (car applications) in this case the voltage regulator v_reg regulates vs3v_avcc to typically 3.0v. if the voltage regul ator is active, a blocking capacitor of 2.2f has to be connected to vs3v_avcc (see figure 10-1 on page 25 ). dvcc is the internal operating voltage of the digital cont rol logic and is fed via the switch sw_dvcc by vs3v_avcc. dvcc must be blocked on pin dvcc with 68nf (see figure 9-1 on page 24 and figure 10-1 on page 25 ). pin rx is the input to activate the rx signal processing and set the receiver to active mode. rssi rx sense_ctrl data_out ask_nfsk enable v th_red t startup_sig_proc v_reg 3.0v typ. sw_dvcc out rx dvcc vs5v vs3v_avcc in en
ata8201/ata8202 [datasheet] 4971g?indco?09/14 18 5.1 off mode a low level on pin rx and enable will set the receiver to off mode (low power mode). in this mode, the crystal oscillator is shut down and no clock is available on pin clk_out. the rece iver is not sensitive to a transmitter signal in this mode. 5.2 standby mode the receiver activates the standby mode if pin enable is set to ?1?. in standby mode, the xto is running and the clock on pin clk_ out is available after the start-up time of the xto has elapsed (dependent on pin clk_out_ctrl0 and clk_out_ctrl1) . during standby mode, the receiver is not sensitive to a transmitter signal. in standby mode, the rx signal path is disabled and the power consumption i standby is typically 50 a (clk_out output off, vs3v_avcc = vs5v = 3v). the exact value of this current is strongly dependent on the applic ation and the exact operation mode, therefore check the section ?electrical characteristic s: general? on page 26 for the appropriate application case. figure 5-2. standby mode (clk_out_ctrl0 or clk_out_ctrl1 = 1) 5.3 active mode the active mode is enabled by setting the level on pin rx to high. in active mode, the rx signal path is enabled and if a valid signal is present it will be transf erred to the connected microcontroller. during t startup_pll the pll is enabled and starts up . if the pll is locked, the signa l processing circuit starts up (t startup_sig_proc ). after the start-up time, all circuits are in stable c ondition and ready to receive. the duration of the start-up sequence depends on the selected bit rate range. table 5-1. standby mode rx enable function 0 0 off mode table 5-2. standby mode rx enable function 0 1 standby mode clk_out enable standby mode t xto_startup table 5-3. active mode rx enable function 1 1 active mode
19 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 5-3. active mode table 5-4. start-up time br1 br0 atmel ata8202 (433.92mhz) atmel ata8201 (315mhz) t startup_pll t startup_sig_proc t startup_pll t startup_sig_proc 0 0 261s 1096s 269s 1132s 0 1 644s 665s 1 0 417s 431s 1 1 304s 324s table 5-5. modulation scheme ask_nfsk rf in at pin lna_in level at pin data_out 0 f fsk_h 1 f fsk_l 0 1 f ask on 1 f ask off 0 data_out valid t startup_pll t startup_sig_proc i startup_pll i active i active i standby startup clk_out rx data_out enable standby mode active mode
ata8201/ata8202 [datasheet] 4971g?indco?09/14 20 6. bit rate ranges configuration of the bit rate ranges is ca rried out via the two pins br0 and br1. the microcontroller uses these two interface lines to set the corner frequencies of the band-pass data filter. switching the bit rate ranges while the rf front end is in active mode can be done on the fly and will not take longer than 100 s if done while remaining in either ask or fsk mode. if the modulation scheme is changed at the same time, the switching time is (t startup_sig_proc , see figure 7-1 on page 22 ). each br_range is defined by a minimum edge-to-edge time. to maintain full sensitivity of the receiver, edge-to-edge transition times of incoming data should not be less than the minimum for the selected br_range. table 6-1. br ranges ask br1 br0 br_range recommended bit rate (manchester) (1) minimum edge-to-edge time period t ee of the data signal (2) edge-to-edge time period t ee of the data signal during the start-up period (3) 0 0 br_range0 1.0kbit/s to 2.5kbits/s 200s 200s to 500s 0 1 br_range1 2.0kbits/s to 5.0kbits/s 100s 100s to 250s 1 0 br_range2 4.0kbits/s to 10.0kbits/s 50s 50s to 125s 1 1 br_range3 8.0kbits/s to 10.0kbits/s 50s 50s to 62.5s table 6-2. br ranges fsk br1 br0 br_range recommended bit rate (manchester) (1) minimum edge-to-edge time period t ee of the data signal (2) edge-to-edge time period t ee of the data signal during the start-up period (3) 0 0 br_range0 1.0kbit/s to 2.5kbits/s 200s 200s to 500s 0 1 br_range1 2.0kbits/s to 5.0kbits/s 100s 100s to 250s 1 0 br_range2 4.0kbits/s to 10.0kbits/s 50s 50s to 125s 1 1 br_range3 8.0kbits/s to 20.0kbits/s 25s 25s to 62.5s note: if during the start-up period (t startup_pll +t startup_sig_proc ) there is no rf signal, the data filter settles to the noise floor, leading to noise on pin data_out. notes: 1. as can be seen, a bit stream of, for example, 2.5kbits/s can be received in br_range0 and br_range1 (overlapping br_ranges). to get the full sensitivit y, always use the lowest possible br_range (here, br_range0). the advantage in the next higher br_range (b r_range1) is the shorter start-up period, mean- ing lower current consumption during polling mode. thus, it is a decision between sensitivity and current consumption. 2. the receiver is also capable of receiving non-man chester-modulated signals, su ch as pwm, ppm, vpwm, nrz. in ask mode, the heade r and blanking periods occurring in k eeloq-like protocols (up to 52ms) are supported. 3. to ensure an accurate settling of the data filter during the start-up period ( t startup_pll + t startup_sig_proc ), the edge-to-edge time t ee of the data signal (preamble) must be inside the given limits during this period.
21 ata8201/ata8202 [datasheet] 4971g?indco?09/14 figure 6-1. examples of supported modulation formats figure 6-2. supported header and blanking periods t ee logic 1 nrz: logic 0 t ee t ee t ee t ee t ee logic 1 ppm: logic 0 t ee t ee t ee t ee t ee t ee logic 1 pwm: logic 0 t ee t ee t ee t ee t ee logic 1 man: logic 0 t ee t ee t ee logic 1 logic 0 vpwm: on transition low to high t ee t ee t ee t ee logic 1 logic 0 on transition high to low preamble header data burst guard time data burst
ata8201/ata8202 [datasheet] 4971g?indco?09/14 22 7. ask_nfsk the ask_nfsk pin allows the microcontroller to rapidly switch the rf front end between demodulation modes. a logic 1 on this pin selects ask mode, and a logic 0 fsk mode. the time to change modes (t startup_sig_proc ) depends on the bit rate range being selected (not current bit rate range) and is given in table 5-4 on page 19 . this response time is specified for applications that require an ask preamb le followed by fsk da ta (for typical tpm app lications). during t startup_sig_proc , the level on pin data_out is low. figure 7-1. ask preamble 2.4kbits/s followed by fsk data 9.6kbits/s rx ask_nfsk data_out data valid br3 data valid br0 br0 br1 enable t startup_sig_proc
23 ata8201/ata8202 [datasheet] 4971g?indco?09/14 8. polling current calculation figure 8-1. polling cycle in an industrial or aftermarket rke and tpm syst em, the average chip curre nt in polling mode, i polling , is an important parameter. the polling period must be cont rolled by the connected microcontroller via the pins enable and rx. the polling current can be calculated as follows: i polling =(t startup_pll /t polling_period ) i startup_pll +(t startup_sig_proc /t polling_period ) i active + (t bitcheck /t polling_period ) i active +(t polling_period ?t startup_pll ?t startup_sig_proc ?t bitcheck )/ t polling_period i standby t startup_pll : depends on 315mhz/433.92mhz application. t startup_sig_proc : depends on 315mhz/433.92mhz application and the selected bit rate range. t bitcheck : depends on the signal bit rate (1 / signal_bit_rate). t polling_period : depends on the transmitter telegram (preburst). i startup_pll : depends on 3v or 5v application and the setting of pin clk_out. i active : depends on 3v or 5v application, ask or fsk mode and the setting of pin clk_out. i standby : depends on 3v or 5v application and the setting of pin clk_out. example:- 315-mhz application (ata8201), bit rate: 9.6kbits/s, t polling_period =8ms --> t startup_pll = 269s --> t startup_sig_proc = 324s (bit rate range 3) --> t bitcheck = 104s 3v application; ask mode, clk_out disabled --> i startup_pll =4.5ma --> i active =6.5ma --> i standby = 0.05ma --> i polling = 0.545ma i standby i standby i active i startup_pll i active i startup_pll rx i supply enable t bitcheck (= 1 / signal_bitrate (average) t startup_pll (startup rf-pll) t startup_sig_proc (startup signal processing)
ata8201/ata8202 [datasheet] 4971g?indco?09/14 24 9. 3v application figure 9-1. 3v application note: paddle (backplane) must be connected to gnd test2 test1 enable clk_out vs5v gnd vs3v_avcc dvcc xtal1 xtal2 br1 rx br0 ask_nfsk cdem data_out clk_out_ctrl0 clk_out_ctrl1 output output output output input output vcc vss test3 lna_in lna_gnd sense sense_ctrl rssi rf in 18pf microcontroller ata8201/ ata8202 18pf 68nf 15nf 2.2pf 68nh/36nh 315mhz/433.92mhz 68nf v cc = 2.7v to 3.3v
25 ata8201/ata8202 [datasheet] 4971g?indco?09/14 10. 5v application figure 10-1. 5v application with reduced/full sensitivity note: paddle (backplane) must be connected to gnd test2 test1 enable clk_out vs5v gnd vs3v_avcc dvcc xtal1 xtal2 br1 rx br0 ask_nfsk cdem data_out clk_out_ctrl0 clk_out_ctrl1 output output output output output input output vcc vss test3 lna_in lna_gnd sense sense_ctrl rssi rf in r sense 18pf microcontroller ata8201/ ata8202 18pf 68nf 15nf 2.2pf 2.2f 68nh/36nh 315mhz/433.92mhz 68nf v cc = 4.5v to 5.5v
ata8201/ata8202 [datasheet] 4971g?indco?09/14 26 11. absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability . parameters symbol min. max. unit junction temperature t j +150 c storage temperature t stg ?55 +125 c ambient temperature t amb ?40 +85 c supply voltage vs5v v s +6 v esd (human body model esd s 5.1) every pin hbm ?4 +4 kv esd (machine model jedec a115a) every pin mm ?200 +200 v esd (field induced charge device model esd stm 5.3.1-1999) every pin fcdm ?500 +500 v maximum input level, input matched to 50 p in_max 0 dbm 12. thermal resistance parameters symbol value unit junction ambient r thja 35 k/w 13. electrical characteristics: general all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* 1 off mode 1.1 supply current in off mode v vs3v_avcc =v vs5v 3v v vs5v =5v clk_out disabled 10, 11 10 i soff 4 4 a a a a 2 standby mode 2.1 supply current standby mode xto running v vs3v_avcc =v vs5v 3v clk_out disabled 10,11 i standby 50 100 a a xto running v vs5v =5v clk_out disabled 10,11 i standby 50 100 a a 2.2 system start-up time xto startup xtal: c m =5ff, c 0 = 1.8pf, r m =15 t xto_startup 0.3 ms a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
27 ata8201/ata8202 [datasheet] 4971g?indco?09/14 2.3 active mode start-up time from standby mode to active mode br_range_3 atmel ata5745 atmel ata5746 t startup_pll + t startup_sig_pro c 565 593 s s a 3 active mode 3.1 rf operating frequency range atmel ata8201 14 f rf 313 317 mhz a atmel ata8202 14 f rf 433 435 mhz a 3.2 supply current active mode v vs3v_avcc =v vs5v =3v ask mode clk_out disabled sense_ctrl = 0 10,11 i active 6.5 ma a v vs3v_avcc =v vs5v =3v fsk mode clk_out disabled sense_ctrl = 0 10,11 i active 6.7 ma a v vs5v =5v ask mode clk_out disabled sense_ctrl = 0 10 i active 6.7 ma a v vs5v =5v fsk mode clk_out disabled sense_ctrl = 0 10 i active 6.9 ma a 3.3 supply current polling mode v vs3v_avcc =v vs5v =3v t polling_period = 8ms br_range_3, ask mode, clk_out disabled data rate = 9.6kbits/s 10,11 i polling 545 a c 3.4 input sensitivity fsk f rf = 315mhz fsk deviation f dev = 38khz ber = 10 ? 3 t amb = 25c bit rate 9.6kbits/s br2 (14) p ref_fsk ?103 ?105 ?106.5 dbm b bit rate 2.4kbits/s br0 (14) p ref_fsk ?106 ?108 ?109.5 dbm b fsk deviation 18khz to 50khz bit rate 9.6kbits/s br2 (14) p ref_fsk ?101 dbm b bit rate 2.4kbits/s br0 (14) p ref_fsk ?104 dbm b 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
ata8201/ata8202 [datasheet] 4971g?indco?09/14 28 3.5 input sensitivity ask f rf = 315mhz ask 100% level of carrier, ber = 10 ? 3 t amb = 25c bit rate 9.6kbits/s br2 (14) p ref_ask ?109 ?111 ?112.5 dbm b bit rate 2.4kbits/s br0 (14) p ref_ask ?112 ?114 ?115.5 dbm b 3.6 sensitivity change at f rf = 433.92mhz compared to f rf = 315mhz f rf = 315mhz to f rf = 433.92mhz p=p ref_ask + p ref1 p=p ref_fsk + p ref1 (14) p ref1 +1 db b 3.7 sensitivity change versus temperature, supply voltage and frequency offset fsk f dev = 38khz f offset 160khz ask 100% f offset 160khz p = p ref_ask + p ref1 + p ref2 p = p ref_fsk + p ref1 + p ref2 (14) p ref2 +4.5 ?1.5 b 3.8 reduced sensitivity r sense connected from pin sense to pin vs3v_avcc p ref_red dbm (peak level) r sense = 62k f in = 433.92mhz ?76 dbm c r sense = 82k f in = 433.92mhz ?88 dbm c r sense = 62k f in = 315mhz ?76 dbm c r sense = 82k f in = 315mhz ?88 dbm c reduced sensitivity variation over full operating range r sense = 62k r sense = 82k p red = p ref_red + p red p red ?10 +10 db 3.9 maximum frequency offset in fsk mode maximum frequency difference of f rf between receiver and transmitter in fsk mode (f rf is the center frequency of the fsk signal with f bit = 10kbits/s f dev = 38khz (14) f offset ?160 +160 khz b 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
29 ata8201/ata8202 [datasheet] 4971g?indco?09/14 3.10 supported fsk frequency deviation with up to 2db loss of sensitivity. note that the tolerable frequency offset is 12khz lower for f dev = 50khz than for f dev = 38khz, hence, f offset 148khz (14) f dev 18 38 50 khz b 3.11 system noise figure f rf = 315mhz (14) nf 6.0 9 db b f rf = 433.92mhz (14) nf 7.0 10 db b 3.12 intermediate frequency f rf = 433.92mhz f if 440 khz a f rf = 315mhz f if 440 khz a 3.13 system bandwidth 3db bandwidth this value is for information only! note that for crystal and system frequency offset calculations, f offset must be used. (14) sbw 435 khz a 3.14 system out-band 3rd-order input intercept point f meas1 = 1.8mhz f meas2 = 3.6mhz f rf = 315mhz (14) iip3 ?24 dbm c f rf = 433.92mhz (14) iip3 ?23 dbm c 3.15 system outband input 1- db compression point f meas1 = 1mhz f rf = 315mhz (14) i1dbcp ?31 ?36 dbm c f rf = 433.92mhz (14) i1dbcp ?30 ?35 dbm c 3.16 lna input impedance f rf = 315mhz 14 z in_lna (72.4 ? j298) c f rf = 433.92mhz 14 z in_lna (55 ? j216) c 3.17 maximum peak rf input level, ask and fsk ber < 10 ? 3 , ask: 100% (14) p in_max +5 ?10 dbm c fsk: f dev = 38khz (14) p in_max +5 ?10 dbm c 3.18 lo spurs at lna_in f < 1ghz (14) ?57 dbm c f >1ghz (14) ?47 dbm c f lo = 315.44mhz 2 f lo 4 f lo (14) ?90 ?94 ?68 dbm c f lo = 434.36mhz 2 f lo 4 f lo (14) ?92 ?88 ?58 dbm c 3.19 image rejection with the complete image band f rf = 315mhz (14) 24 30 db a f rf = 433.92mhz (14) 24 30 db a 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
ata8201/ata8202 [datasheet] 4971g?indco?09/14 30 3.20 useful signal to interferer ratio peak level of useful signal to peak level of interferer for ber < 10 ? 3 with any modulation scheme of interferer fsk br_ranges 0, 1, 2 (14) snr fsk0-2 2 3 db b fsk br_range_3 (14) snr fsk3 4 6 db b ask (p rf < p rfin_high ) (14) snr ask 10 14 db b 3.21 rssi output dynamic range (14),17 d rssi 65 db a lower level of range f rf = 315mhz f rf = 433.92mhz (14),17 p rfin_low ?110 dbm a upper level of range f rf = 315mhz f rf = 433.92mhz (14),17 p rfin_high ?45 dbm a gain (14),17 15 mv/db a output voltage range (14),17 v rssi 350 1675 mv a 3.22 output resistance rssi pin 17 r rssi 8 10 12.5 k c 3.23 blocking sensitivity (ber = 10 ? 3 ) is reduced by 3db if a continuous wave blocking signal at f is p block higher than the useful signal level (bit rate = 10kbits/s, fsk, f dev 38khz, manchester code, br_range2) f rf = 315mhz f 1.5mhz f 2mhz f 3mhz f 10mhz f 20mhz (14) p block 57.5 63.0 67.5 72.0 74.0 dbc c f rf = 433.92mhz f 1.5mhz f 2mhz f 3mhz f 10mhz f 20mhz (14) p block 56.5 62.0 66.5 71.0 73.0 dbc c 3.24 cdem capacitor connected to pin 23 (cdem) 23 ?5% 15 +5% nf d 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
31 ata8201/ata8202 [datasheet] 4971g?indco?09/14 4 xto 4.1 transconductance xto at start at startup; after startup the amplitude is regulated to v ppxtal 7,8 g m, xto 20 ms b 4.2 xto start-up time c 0 2.2pf c m < 14ff r m 120 7,8 t xto_startup 300 s a 4.3 maximum c 0 of xtal 7,8 c 0max 3.8 pf d 4.4 pulling of lo frequency f lo due to xto, c l1 and c l2 versus temperature and supply changes 1.0pf c 0 2.2pf c m = 4.0ff to 7.0ff r m 120 3 f xto ?5 +5 ppm c 4.5 amplitude xtal after startup c m = 5ff, c 0 =1.8pf r m = 15 v(xtal1, xtal2) peak-to-peak value 7,8 v ppxtal 700 mvpp c v(xtal1) peak-to-peak value 7,8 v ppxtal 350 mvpp c 4.6 maximum series resistance r m of xtal at startup c 0 2.2pf, small signal start impedance, this value is important for crystal oscillator startup 7,8 z xtal12_start ?1400 ?2000 b 4.7 maximum series resistance r m of xtal after startup c 0 2.2pf c m < 14ff 7,8 r m_max 15 120 b 4.8 nominal xtal load resonant frequency f rf = 433.92mhz f rf =315mhz 7,8 f xtal 13.57375 13.1433 mhz d 4.9 external clk_out frequency clk_out_crtl1 = 0 clk_out_ctrl0 = 0 --> clk_out disabled 3 f clk_out f clk disabled (low level on pin clk_out) mhz a clk_out_crtl1 = 0 clk_out_ctrl0 = 1 --> division ratio = 3 clk_out_crtl1 = 1 clk_out_ctrl0 = 0 --> division ratio = 6 clk_out_crtl1 = 1 clk_out_ctrl0 = 1 --> division ratio = 12 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ). f clk f xto 3 ----------- = f clk f xto 6 ----------- = f clk f xto 12 ----------- =
ata8201/ata8202 [datasheet] 4971g?indco?09/14 32 f rf = 433.92mhz clk_out division ratio = 3 = 6 = 12 clk_out has nominal 50% duty cycle 3 f clk_out 4.52458 2.26229 1.13114 mhz d f rf =315mhz clk_out division ratio = 3 = 6 = 12 clk_out has nominal 50% duty cycle 3 f clk_out 4.3811 2.190 1.0952 mhz d 4.10 dc voltage after startup v dc (xtal1, xtal2) xto running (standby mode, active mode) 7,8 v dcxto ?250 ?45 mv c 5 synthesizer 5.1 spurs in active mode at f clk_out , clk_out enabled (division ratio = 3) f rf =315mhz f rf = 433.92mhz sp rx ?75 ?70 dbc c at f xto f rf =315mhz f rf = 433.92mhz sp rx ?75 ?70 dbc a 5.2 phase noise at 3 mhz active mode f rf =315mhz f rf = 433.92mhz l rx3m ?130 ?127 dbc/hz a 5.3 phase noise at 20 mhz active mode noise floor l rx20m ?135 ?132 dbc/hz b 6 microcontroller interface 6.1 clk_out output rise and fall time f clk_out <4.5mhz c l =10pf c l = load capacitance on pin clk_out 2.7v v vs5v 3.3v or 4.5v v vs5v 5.5v 20% to 80% v vs5v 3 t rise t fall 20 20 30 30 ns ns c 6.2 internal equivalent capacitance used for current calculation 3 c clk_out 8 pf c 13. electrical characteristics: general (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc =v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 315mhz unless otherwise specified. details about current consumption, timing, and digi tal pin properties can be found in the specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin (1) symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter note: 1. pin numbers in parenthesis were measured with rf_in matched to 50 according to figure 2-1 on page 6 with compo- nent values as in table 2-2 on page 7 (rf in ).
33 ata8201/ata8202 [datasheet] 4971g?indco?09/14 14. electrical characteristic: 3v application all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin symbol min. typ. max. unit type* 7 3v application 7.1 supply current in off mode v vs3v_avcc =v vs5v 3v clk_out disabled 10, 11 i soff 2 a a 7.2 current in standby mode (xto is running) v vs3v_avcc = v vs5v 3v external load c on pin clk_out = 12pf clk enabled (division ratio 3) clk enabled (division ratio 6) clk enabled (division ratio 12) clk disabled 10, 11 i standby 420 290 220 50 a c c c a 7.3 current during t startup_pll v vs3v_avcc = v vs5v 3v clk disabled 10, 11 i startup_pll 4.5 ma c 7.4 current in active mode ask v vs3v_avcc = v vs5v 3v clk disabled sense_ctrl = 0 10, 11 i active 6.5 ma a 7.5 current in active mode fsk v vs3v_avcc = v vs5v 3v clk disabled sense_ctrl = 0 10, 11 i active 6.7 ma a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata8201/ata8202 [datasheet] 4971g?indco?09/14 34 15. electrical characteristics: 5v application all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?e lectrical characteristics?. no. parameters test conditions pin symbol min. typ. max. unit type* 8 5v application 8.1 supply current in off mode v vs5v =5v clk_out disabled 10 i soff 2 a a 8.2 current in standby mode (xto is running) v vs5v 5v external load c on pin clk_out = 12pf clk enabled (division ratio 3) clk enabled (division ratio 6) clk enabled (division ratio 12) clk disabled 10 i standby 700 490 370 50 a c c c a 8.3 current during t startup_pll v vs5v =5v clk disabled 10 i startup_pll 4.7 ma c 8.4 current in active mode ask v vs5v =5v clk disabled sense_ctrl = 0 10 i active 6.7 ma a 8.5 current in active mode fsk v vs5v =5v clk disabled sense_ctrl = 0 10 i active 6.9 ma a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
35 ata8201/ata8202 [datasheet] 4971g?indco?09/14 16. digital timing characteristics all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?electrical characteristics? no. parameters test conditions pin symbol min. typ. max. unit type* 9 basic clock cycle of the digital circuitry 9.1 basic clock cycle t dclk 16 / f xto 16 / f xto s a 9.2 extended basic clock cycle br_range_0 br_range_1 br_range_2 br_range_3 t xdclk 8 4 2 1 t dclk 8 4 2 1 t dclk s a 10 active mode 10.1 startup pll t startup_pll 15 s + 208 t dclk s a 10.2 startup signal processing br_range_0 br_range_1 br_range_2 br_range_3 t startup_sig_proc 929.5 545.5 353.5 257.5 t dclk 929.5 545.5 353.5 257.5 t dclk a 10.3 bit rate range ask br_range = br_range0 br_range1 br_range2 br_range3 fsk br_range = br_range0 br_range1 br_range2 br_range3 br_range 1.0 2.0 4.0 8.0 1.0 2.0 4.0 8.0 2.5 5.0 10.0 10.0 2.5 5.0 10.0 20.0 kbits/s a 10.4 minimum time period between edges at pin data_out br_range_0 br_range_1 br_range_2 br_range_3 24 t data_out_min 10 t xdclk s a 10.5 edge-to-edge time period of the data signal for full sensitivity in active mode br_range_0 br_range_1 br_range_2 br_range_3 t data_out 200 100 50 25 500 250 125 62.5 s b *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata8201/ata8202 [datasheet] 4971g?indco?09/14 36 17. digital port characteristics all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?electrical characteristics? no. parameters test conditions pin symbol min. typ. max. unit type* 11 digital ports 11.1 enable input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 6 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 6 v ih 0.8 v s v a 11.2 rx input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 19 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 19 v ih 0.8 v s v a 11.3 br0 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 20 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 20 v ih 0.8 v s v a 11.4 br1 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 21 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 21 v ih 0.8 v s v a 11.5 ask_nfsk input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 22 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 22 v ih 0.8 v s v a *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
37 ata8201/ata8202 [datasheet] 4971g?indco?09/14 11.6 sense_ctrl input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 16 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 16 v ih 0.8 v s v a 11.7 clk_out_ctrl0 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 5 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 5 v ih 0.8 v s v a 11.8 clk_out_ctrl1 input - low level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 4 v il 0.2 v s 0.12 v s v a - high level input voltage v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v 4 v ih 0.8 v s v a 11.9 test1 input test1 input must always be connected directly to gnd 2 0 0 v d 11.10 test2 output test2 output must always be connected directly to gnd 1 0 0 v d 11.11 test3 input test3 input must always be connected directly to gnd 18 0 0 v d 17. digital port characteristics (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?electrical characteristics? no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
ata8201/ata8202 [datasheet] 4971g?indco?09/14 38 11.12 data_out output - saturation voltage low v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = 250a 24 v ol 0.15 0.4 v b - saturation voltage high v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = ?250a 24 v oh v vs ? 0.4 v vs ? 0.15 v b 11.13 clk_out output - saturation voltage low v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = 100a 3 v ol 0.15 0.4 v b - saturation voltage high v s = v vs3v_avcc = v vs5v = 2.7v to 3.3v v s = v vs5v = 4.5v to 5.5v i data_out = ?100a 3 v oh v vs ? 0.4 v vs ? 0.15 v b 17. digital port characteristics (continued) all parameters refer to gnd and are valid for t amb = 25c, v vs3v_avcc = v vs5v = 3v, and v vs5v = 5v. typical values are given at f rf = 433.92mhz unless otherwise specif ied. details about current consumption, timing, and digital pin properties can be found in th e specific sections of the ?electrical characteristics? no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation test ed, c = characterized on samp les, d = design parameter
39 ata8201/ata8202 [datasheet] 4971g?indco?09/14 19. package information 18. ordering information extended type number package moq remarks ata8202c-pxqw-1 qfn24 6000pcs 5mm 5mm, pb-free, 433.92mhz ata8201c-pxqw-1 qfn24 6000pcs 5mm 5mm, pb-free, 315mhz package drawing contact: packagedrawings@atmel.com gpc drawing no. rev. title 6.543-5132.02-4 1 10/18/13 package: vqfn_5x5_24l exposed pad 3.6x3.6 common dimensions (unit of measure = mm) min nom note max symbol dimensions in mm specifications according to din technical drawings 0.035 0.05 0.0 a1 55.1 4.9 e 0.25 0.3 0.2 b 0.65 e 0.4 0.45 0.35 l 3.6 3.7 3.5 e2 3.6 3.7 3.5 d2 55.1 4.9 d 0.21 0.26 0.16 a3 0.85 0.9 0.8 a top view d 24 1 6 pin 1 id e side view a3 a a1 b l z 10:1 bottom view e d2 24 19 7 1 6 12 13 18 e2 z
ata8201/ata8202 [datasheet] 4971g?indco?09/14 40 20. revision history please note that the following page numbers re ferred to in this section re fer to the specific revision mentioned, not to this document. revision no. history 4971g-indco-09/14 ? section 18 ?ordering inform ation? on page 39 updated ? section 19 ?package information? on page 39 updated 4971f-indco-07/14 ? put datasheet in the latest template 4971e-indco-12/12 ? section 18 ?ordering inform ation? on page 39 changed 4971d-indco-07/12 ? section 13 ?electrical characteristics: general? on pages 26 to 32 changed ? section 14 ?electrical characteristic: 3v application? on page 33 changed ? section 15 ?electrical characteristic: 5v application? on page 34 changed ? section 18 ?ordering inform ation? on page 39 changed 4971c-indco-04/09 ? put datasheet in the newest template ? benefits on page 2 updated 4971b-indco-10/07 ? put datasheet in the newest template
x x xx x x atmel corporation 1600 technology drive, san jose, ca 95110 usa t: (+1)(408) 441.0311 f: (+1)(408) 436.4200 | www.atmel.com ? 2014 atmel corporation. / rev.: rev.: 4971g?indco?09/14 atmel ? , atmel logo and combinations thereof, enabling unlimited possibilities ? , and others are registered trademarks or trademarks of atmel corporation in u.s. and other countries. other terms and product names may be trademarks of others. disclaimer: the information in this document is provided in c onnection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in the atmel terms and condit ions of sales located on the atmel website, atmel assumes no liability wh atsoever and disclaims any express, implied or statutory warranty relating to its p roducts including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, pu nitive, special or incidental damages (including, without limi tation, damages for loss and profits, business interruption, or loss of information ) arising out of the use or inability to use this document, even if atmel has been advised of the possibility of such damages. atmel makes no r epresentations or warranties with respect to the accuracy or c ompleteness of the contents of this document and reserves the right to make changes to specificatio ns and products descriptions at any time without notice. atmel d oes not make any commitment to update the information contained herein. unless specifically provided otherwise, atme l products are not suitable for, and shall not be used in, automo tive applications. atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. safety-critical, military, and automotive applications disclaim er: atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to re sult in significant personal inju ry or death (?safety-critical a pplications?) without an atmel officer's specific written consent. safety-critical applications incl ude, without limitation, life support devices and systems, equipment or systems for t he operation of nuclear facilities and weapons systems. atmel products are not designed nor intended for use in military or aerospace applications or environments unless specifically designated by atmel as military-grade. atmel products are not designed nor intended for use in automot ive applications unless spec ifically designated by atmel as automotive-grade.

▲Up To Search▲

Price & Availability of ATA8202-14

	To Download ATA8202-14 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .